Performance Simulator for RISC-V Processor Architecture
The RISC-V ecosystem is gaining popularity in the industry due to its open-source nature. There are simulation platforms at various levels (functional, formal, and FPGA), but currently, there’s a gap in having a simulation platform at the cycle level. The gem5 simulator, a well-known cycle-level simulation platform, addresses this gap and provides various features to measure performance at the cycle level. In our FYP, the performance of the RISC-V architecture is measured using gem5 CPU models (TimingSimpleCPU, O3CPU, and In-Order MinorCPU) and the Visionfive2 Single Board Computer. Detailed performance metrics such as pipelining, out-of-order execution, and branch prediction, including CPU parameters such as IPC (Instructions Per Cycle), execution time, and cache hit/miss rates, are observed. The results show that TimingSimpleCPU has lower performance than all other CPU models because it is a single-cycle CPU. While MinorCPU, which is an in-order pipelined model, has greater performance results than TimingSimpleCPU. The O3CPU spends fewer cycles on instructions, and its IPC, CPI, and other performance metrics are significantly better. The Visionfive 2 Single Board Computer breaks the instruction into small instructions, so it spends more cycles, but its IPC rate is better than other CPU models.
Keywords: gem5,RISC-V,Performance Simulator,VisionFive 2 Single Board Computer
Tools: gem5,riscv64,VisionFive2
Department: Department of Electrical Engineering
Project Team Members
| Name |
Email |
|
Uroosa Iftikhar
|
uroosa2020@namal.edu.pk |
|
Abdul Qadeer
|
qadeer2020@namal.edu.pk |
|
Muhammad Ayyaz
|
ayaz2020@namal.edu.pk |
Project Poster
