This project integrates the Bit-Manipulation extension into the RISC-V SweRV EH1 Core to enhance performance, security, and efficiency in embedded systems and IoT applications. The team has designed the microarchitecture, modified the RTL, and conducted functional verification using industry-standard tools. Modified code will be ported to an FPGA for implementation and synthesis and testing will be carried out on various real life applications .
Keywords: RISC-V, SweRV EH1 Core, Micro-architecture, Bit Manipulation, Embedded Applications, Performance, Efficiency, Security
Tools: Tools: Verilator, GCC Toolchain, Xilinx Tools like Vivado,Technologies: System Verilog, Verilog, C/C++,Techniques: Functional Verification, Performance Analysis
Department: Department of Electrical Engineering
Tools: Tools: Verilator, GCC Toolchain, Xilinx Tools like Vivado,Technologies: System Verilog, Verilog, C/C++,Techniques: Functional Verification, Performance Analysis
Department: Department of Electrical Engineering
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