Integration and Verification of L1 Data Cache in SweRV EH1 RISC-V Core
RISC-V is a new open-source instruction set architecture (ISA) in computing processor technology. It has fueled billions of cores to be built on this ISA. SweRV EH1 is an open-source core developed by Western Digital. It is a 32-bit, dual-issue, superscalar, in-order, 9-stage pipeline core that supports the RV32IMC ISA. The core lacks a data cache, whose presence increases the core’s performance by reducing the main memory access time. This project aims to add the Data Cache (D-Cache) to the SweRV EH1, a RISCV processor architecture-based core, in order to enhance its performance. Cache is a small, fastest memory connected closest to the CPU, which stores the frequently used data required from the main memory. Modern CPUs aren’t directly connected to main memory; instead, they rely on a smaller, faster on-chip (usually level 1) or off-chip memory named cache. This project is our contribution to open source hardware: Implementation of a parameterized set-associative Level 1 data cache with a Least Recently Used (LRU) replacement policy. The next phase of the project includes integration of the cache into the core along with the DCCM (Data Closely Coupled Memory), connected via the AXI4 bus (memory communication protocol). Verification of the core with cache and performance analysis against various test programs, including Coremark and Dhrystone.
Keywords: RISC-V, Data Cache, Latency, Parameterized, Set-Associative, SweRV EH1, Cache Controller,AXI4
Tools: RISCV,LINUX,SYSTEMVERILOG,VERILATOR,XILINX,OPEN SOURCE HARDWARE ,GITHUB,VS CODE
Department: Department of Electrical Engineering
Project Team Members
| Name |
Email |
|
Ahmed Maroof
|
ahmedmaroof2020@namal.edu.pk |
|
Majid Ali
|
majid2020@namal.edu.pk |
Project Poster
.png)