Trojan Detection in RISC-V
The final year project “Trojan Detection in RISC-V” aims to improve the security of RISC-V processors, which are increasingly used in embedded systems and IoT devices. The project focuses on protecting RISC-V systems from malicious attacks, particularly Trojans, and targets Control Hijack, Return Oriented Programming (ROP) and Buffer Overflow attacks. The approach is to examine the code for suspicious behavior to preemptively thwart Trojans. The three key strategies suggested for detecting and preventing Trojans include encryption to secure vulnerable memory areas, hashing to verify code and data integrity, and memory access pattern protection to monitor and contain abnormal behavior. Successful execution of buffer overflow and control hijack attacks on DarkRiscv and VeerEL2 RISC-V cores using Verilator and Iverilog simulators revealed different levels of vulnerabilities. While sections such as ALU, PC and muxes are relatively safe, I/O, buses and memory areas prove to be vulnerable. We are currently working on developing a robust Trojan detection algorithm for RISC-V cores, contributing to the further development and widespread adoption of open source ISA in security-critical applications.In line with Sustainable Development Goal 9, the project aims to strengthen the security and reliability of RISC-V technology, which is critical for innovative embedded systems and IoT applications.
Keywords: RISC-V Security,Malware Protection in RISC-V,Cybersecurity in Embedded Systems,Open-Source ISA Security,Secure RISC-V Implementations,Secure Coding Practices for RISC-V
Tools: C,verilog,system verilog,GCC,RISC-V,Verilator,Iverlog
Department: Department of Electrical Engineering
Project Team Members
| Name |
Email |
|
Sohaib Hussain
|
sohaib2020@namal.edu.pk |
|
Maheen Gul
|
maheen2020@namal.edu.pk |
Project Poster
