Design of RISC-V AI Accelerator using MLIR-Based IREE Compiler

This project designs and implements a hardware-software co-design framework for AI inference on RISC-V architecture using the MLIR-based IREE compiler toolchain. A two-stage cross-compilation pipeline is established on a host system, producing RISC-V compatible deployable binaries, with correctness verified through matrix multiplication tests executed on the VisionFive 2 RISC-V board. In the final application stage, a pre-trained classification model is loaded using the ONNX inference framework in Python and deployed on the VisionFive 2 for real-time image classification. Inference performance is benchmarked under two conditions: without the AI accelerator and with the compiler-driven AI accelerator applied measuring inference speed (images classified per second) and speedup ratio (how many times faster the accelerated pipeline runs over the baseline) as the key performance indicators, providing concrete proof of concept that compiler-integrated acceleration meaningfully improves AI inference on resource-constrained open RISC-V hardware. The entire solution relies on open-source tools and affordable hardware, aligned with UN SDG 9 (Industry, Innovation, and Infrastructure).

Poster