This project focuses on improving processor performance by reducing instruction fetch latency in the SweRV EH1 RISC-V core. The processor suffers delays during instruction cache misses, which impacts overall pipeline efficiency. To address this, a stream buffer-based instruction prefetcher is designed and integrated into the Instruction Fetch Unit (IFU). The prefetcher predicts sequential instruction streams and fetches future cache lines in advance using an AHB-Lite burst interface. The proposed design includes a four-entry stream buffer capable of storing full cache lines and handling speculative execution and control flow changes. By reducing cache miss penalties, the system improves throughput and enhances overall processor performance with minimal hardware overhead.
Tools: RISCV,Linux, System Verilog, Verilator, Github, Open Source Hardware
Department: Department of Electrical Engineering
Poster
